1. Field of the Invention
The present invention relates to a method and apparatus for controlling the phase of a system clock that is synchronized with an external clock, and more particularly to a method and apparatus for controlling the phase of a system clock when an external clock is intercepted or recovered.
2. Description of the Related Art
There is known an effective conventional means for synchronizing a network such as a local area network (LAN) with a public digital network of NTT or the like connected to LAN. With this means, an external clock is supplied to a phase-locked loop (PLL) and frequency-divided to 8 kHz which is the greatest common divisor between 1.544 Mbps of a high speed digital interface of the public digital network and 2.028 Mbps of a PBX interface of LAN. This 8 kHz signal phase-locked in PLL is supplied as clock information to each node of LAN, after high frequency jitters (fluctuation at clock edges) are eliminated at PLL.
FIG. 1 is a block diagram showing an example of the circuit structure of PLL. Reference numeral 21 represents a phase comparator, reference numeral 22 represents a low-pass filter (LPF), reference numeral 23 represents a voltage-controlled oscillator (VCO), and reference numeral 24 represents a frequency divider having a division ratio N (N is an integer).
In PLL shown in FIG. 1, the phase comparator 21 compares the phase of a clock 38 supplied from the external network to that of an output of the frequency divider 24 (this output is called a PLL output clock, hereinafter where applicable). An output 27 of the phase comparator 21 is smoothed by LPF 22 and output as a voltage signal 28 which controls VCO 23 to oscillate a predetermined frequency signal 29.
VCO 23 is an oscillator whose oscillation frequency is controlled by a voltage 28 output from LPF 22. The frequency of an output 29 of VCO 23 is divided by N by the frequency divider 24. An output 25 of the frequency divider 24 is used as a system clock of LAN (not shown) if the external clock is normal.
In PLL described above, if the frequency of VCO 23 changes the frequency of the PLL output clock 25 also changes. However, this frequency change reduces the output 27 of the phase comparator 21 so that the phase difference between the clock 38 from the external network and the PLL output clock 25 gradually reduces to eventually synchronize both of the clocks. The frequency of the VCO output is generally set N (an arbitrary integer) times as high as that of the clock from the external network.
If the clock 38 from the external network is not supplied to PLL, the output 29 of VCO 23 takes its self-running oscillation frequency. The self-running oscillation frequency of VCO 23 has, in some cases a shift of 10% or more from that under the phase-locked state. In this case, the PLL output clock 25 from the frequency divider 24 also has the shift of 10% or more, and is difficult to be used as the system clock.
Even when the clock 38 from the external network is not supplied, the system is requested to maintain communications within the LAN. Therefore, it is necessary to provide the system clock with the compensated frequency shift even when the external clock is intercepted.
A conventional technique for satisfying such conditions is known as described, for example, in JP-A-1-180151.
FIG. 2 is a block diagram showing the circuit of this conventional technique. Reference numeral 30 represents an internal clock standard oscillator, reference numeral 41 represents a selector, and reference numeral 54 represents an external clock interception detector. Other elements are similar to those shown in FIG. 1 and represented by identical reference numerals, and so the description thereof is omitted.
The conventional technique illustrated in FIG. 2 has the internal clock standard oscillator 30, external clock interception detector 54, and selector 41 for selecting one of the external and internal clocks, respectively added to PLL shown in FIG. 1.
If the external clock 38 is intercepted, the external clock interception detector 54 detects this interception and inputs the clock interception information to the selector 41 connected to the front stage of the phase comparator 21. The selector 41 then selects the internal clock 37 instead of the external clock 38.
Since the internal clock 37 phase-locked by PLL has no frequency shift, it can be used as the system clock even when the external clock is intercepted. Furthermore, when the external clock is recovered, clock recovery information is supplied from the external clock interception detector 54 to the selector 41 at the front stage of the phase comparator 21. The selector 41 then selects the external clock 38 instead of the internal clock 37, to synchronize the PLL output clock or system clock with the external clock.
The above-described conventional technique eliminates the frequency shift of the PLL output clock when the external clock is intercepted. However, the phase control is not made at the time of switching from the external clock 38 to the internal clock 37 or vice versa, posing a problem of a phase step of 180 degrees at a maximum.
Therefore, communications within the LAN are temporarily disturbed in some cases, and terminal equipment at each node of LAN is unable to communicate temporarily. This communication disabled period adversely affects terminal equipment, particularly, those equipment requiring real time operation. In addition, as the scale of LAN becomes large, the number of nodes increases so that the communication disable state propagates to the wide range of LAN.